Freescale公司的 i.MX25是用于消費類(lèi)和工業(yè)領(lǐng)域的多媒體應用處理器，采用ARM926EJ-S內核，速度高達具400MHz，具有高性能低功耗特性，支持新興的工業(yè)和通用嵌入市場(chǎng)。i.MX25支持133MHz DDR2存儲器，集成了10/100以太網(wǎng)MAC和兩個(gè)USB PHY，主要用在住宅區網(wǎng)關(guān)，工業(yè)控制，人機接口（HMI），手持掃描儀和打印機，POS，病人監護儀，圖像遙控等。本文介紹了i.MX25多媒體應用處理器主要特性和接口框圖，包括SENNA個(gè)性板，調試板和i.MX25 CPU引擎板在內的i.MX25 PDK硬件開(kāi)發(fā)系統三件套主要特性，方框圖，電路圖和材料清單。
The i.MX25 multimedia applications processor has the right mix of high performance, low power, and integration to support the growing needs of the industrial and general embedded markets. At the core of the i.MX25 is Freescale’s fast, proven, power-efficient implementation of the ARM926EJ-S core, with speeds of up to 400 MHz.
The i.MX25 includes support for up to 133-MHz DDR2 memory, integrated 10/100 Ethernet MAC, and two on-chip USB PHYs. The device is suitable for a wide range of applications, including the following:
• Graphical remote controls
• Human Machine Interface (HMI)
• Residential and commercial control panels
• Residential gateway (smart metering)
• Handheld scanners and printers
• Electronic point-of-sale terminals
• Patient-monitoring devices

i.MX25多媒體應用處理器主要特性：
• Advanced power management—The heart of the device is a level of power management throughout the IC that enables the multimedia features and peripherals to achieve minimum system power consumption in active and various low-power modes. Power management techniques allow the designer to deliver a feature-rich product that requires levels of power far lower than typical industry expectations.
• Multimedia powerhouse—The multimedia performance of the i.MX25 processor is boosted by a 16 KB L1 instruction and data cache system and further enhanced by an LCD controller (with alpha blending), a CMOS image sensor interface, an A/D controller (integrated touchscreen controller), and a programmable Smart DMA (SDMA) controller.
• 128 Kbytes on-chip SRAM—The additional 128 Kbyte on-chip SRAM makes the device ideal for eliminating external RAM in applications with small footprint RTOS. The on-chip SRAM allows the designer to enable an ultra low power LCD refresh.
• Interface flexibility—The device interface supports connection to all common types of external memories: MobileDDR, DDR, DDR2, NOR Flash, PSRAM, SDRAM and SRAM, NAND Flash, and managed NAND.
• Increased security—Because the need for advanced security for tethered and untethered devices continues to increase, the i.MX25 processor delivers hardware-enabled security features that enable secure e-commerce, Digital Rights Management (DRM), information encryption, robust tamper detection, secure boot, and secure software downloads.
• On-chip PHY—The device includes an HS USB OTG PHY and FS USB HOST PHY.
• Fast Ethernet—For rapid external communication, a Fast Ethernet Controller (FEC) is included.
• i.MX25 only supports Little Endian mode.

圖1。i.MX25簡(jiǎn)化接口方框圖

i.MX25多媒體應用處理器硬件設計文件PDK
The i.MX25 3-Stack Platform System helps you to develop multimedia communication applications using the i.MX25 ARM-9 CPU and the MC34704 power management chip.
The 3-Stack consists of a CPU Engine board, a Personality board and a Debug board. The system supports application software development, target board debugging, and optional circuit cards. The CPU board can be run in stand-alone mode for code development. A 5’7 LCD display panel is supplied with the 3-Stack.

圖2。i.MX25 PDK硬件開(kāi)發(fā)系統三件套外形圖

圖3。i.MX25 PDK硬件開(kāi)發(fā)系統三件套主要元器件

i.MX25 PDK硬件開(kāi)發(fā)系統主要特性：
Near form-factor demonstration modules and working platforms.
Solid reference schematics that closely resemble final products to aid customers’ designs.
Three-board system, which includes:
- CPU board with i.MX25 ARM-9 CPU, MC34704 chip
- Personality board with peripheral components and interface connectors
- Debug board with two RS232 interfaces, 10/100 Base-T Ethernet connector, and current measure connectors. 
Utilizes reliable high-density connector to interface between boards.

圖4。i.MX25 PDK硬件開(kāi)發(fā)系統三件套主板外形圖

圖5。SENNA個(gè)性板方框圖

圖6。SENNA個(gè)性板電路圖（1）

圖7。SENNA個(gè)性板電路圖（2）

圖8。SENNA個(gè)性板電路圖（3）

圖9。SENNA個(gè)性板電路圖（4）

圖10。SENNA個(gè)性板電路圖（5）

圖11。SENNA個(gè)性板電路圖（6）

圖12。SENNA個(gè)性板電路圖（7）

圖13。SENNA個(gè)性板電路圖（8）

圖14。SENNA個(gè)性板電路圖（9）

圖15。SENNA個(gè)性板電路圖（10）

圖16。SENNA個(gè)性板電路圖（11）

圖17。SENNA個(gè)性板電路圖（12）

圖18。調試板方框圖

圖19。調試板電路圖（1）

圖20。調試板電路圖（2）

圖21。調試板電路圖（3）

圖22。調試板電路圖（4）

圖23。調試板電路圖（5）

圖24。調試板電路圖（6）

圖25。調試板電路圖（7）

圖26。調試板電路圖（8）

圖27。調試板電路圖（9）

圖28。i.MX25 CPU引擎板方框圖

圖29。i.MX25 CPU引擎板電路圖（1）

圖30。i.MX25 CPU引擎板電路圖（2）

圖31。i.MX25 CPU引擎板電路圖（3）

圖32。i.MX25 CPU引擎板電路圖（4）

圖33。i.MX25 CPU引擎板電路圖（5）

圖34。i.MX25 CPU引擎板電路圖（6）

圖35。i.MX25 CPU引擎板電路圖（7）


圖36。i.MX25 CPU引擎板電路圖（8）